The purpose of a logic probe is to examine the logic states at a particular point in an electronic circuit. It is usually used in fault finding and testing but it can also be used to find out how a piece of electronic equipment works or to assist in electronic design. There are many circuits for this type of probes. Some are very simple while others have added so many features the probe has become too big. At a minimum any probe should be usable with both CMOS and TTL logic families. In this design a pulse detection circuit has been added because the detection of electronic pulses is so important today in many electronic circuits.
Logic Probe Circuit Description
1. There are two main logic families used in electronics: CMOS and TTL. For CMOS the supply voltage may be anywhere between 3V and 15V and the logic levels used are taken as a proportion of the supply voltage. Levels quoted by different manufacturers vary so the the probe should be calibrated for the most extreme cases.)
For CMOS the extreme limits are:
HIGH -- greater than 73.3% of supply voltage
LOW -- less than 26.6% of supply voltage
For TTL the supply voltage should be 5 volts and the logic levels are:
HIGH -- greater than 2 volts
LOW -- less than 0.8 volts
At a minimum a logic probe should be usable over the full range of CMOS circuit voltages. In practice this is from 5V to 15V. If the probe takes its power supply from the circuit under test (as most do) then all components in the probe must operate over the 5 to 15 volt range. Some electronic equipment may have different voltage circuits within it so you must connect to the correct one that you want to test. A good logic probe should be able to detect both positive and negative pulses. It should be able to detect the brief pulses which can switch CMOS and SCR devices. The minimum width of these pulses is of the order of 50 ns (50 nano seconds, 50 x 10-9 seconds.) In this project we have incorporated a high speed, dual polarity pulse detection and stretching circuit which can capture these pulses. Detection is no good without audible and visual indication of what is detected. Audible indication is necessary so that you do not have to take your eyes off where you are working with the tip of the probe. Three different coloured 3mm LED's give a visual indication. The table gives the various combinations of logic levels and pulse widths which can be detected.
2. Logic Probe Circuit Description - Level Detector.
This circuit consists of a dual op-amp and two resistor divider networks which can be selected by a switch. One network selects the voltage levels for CMOS, the other for TTL. The resistor dividers are not protected because the nonlinearity of the diode would affect the level references. The LM358 wide range, single supply, dual op-amp was selected so that it can operate over the full range of CMOS supply voltages. Amp A detects the high level. The inverting input (pin 2) is set to the high level reference. If the noninverting input (pin 3) rises above that level then the output (pin 1) switches to high. This high activates the high level indicators until the level of the input signal is reduced below the high level reference. Amp B performs a similar function for the low level. This time it is the noninverting input (pin 5) that connects to the reference. Accordingly the amp switches high when the input from the probe (pin 6) falls below the low level reference. The low level indicators are then activated until the input voltage is raised above the low level reference again.
3. Logic Probe Circuit Description - Pulse Detector.
This circuit consists of 4 CMOS inverters (in the 4049/14049) and some passive components. Start at pin 7. Usually R15 holds pin 5 low which makes pin 4 high, which in turn makes pin 7 high via diode D4 leakage. If pin 7 is pulled down by a negative pulse from C2 or C3 the pulse travels through the first inverter (and becomes high), then to C4 and the second inverter to arrive at pin 4 as a low. The low holds pin 7 low via diode D4. Pin 6 is now high. Pin 5 is therefore held high until C4 discharges through R15. When pin 5 falls to the CMOS low level pin 4 goes high again and the latch is released. The pulse indication time is set by the time constant C4.R15. When a pulse is detected it is stretched to about a second during which time the orange LED is turned on and a tone sounds. The tone will be a medium tone unless the final level is low. In this case the tone will be a low pitch. Before the pulse detector circuit are two inverters. They perform a number of functions. They shape the level change into a sharp pulse and put out signals at rail voltage. Any change of level (low to high or high to low) at the probe will cause one inverter to go high and the other to go low. By adding the diodes D2 and D3, when a level change occurs the output going from low to high is blocked temporarily until its leakage current charges the 100pF series capacitor. However, the output going from high to low is not blocked because its diode is then forward biased and a negative going pulse arrives at pin 7. As describes in the previous paragraph a negative pulse at pin 7 causes a pulse detection signal. If the input to the logic probe is not in a defined state (that is, if it is in the range 26.6% to 73.3% of the supply voltage for a cmos circuit, or 16% to 40% of the supply voltage for a TTL circuit) then it is in the floating level. However, the cmos gate connected to the probe will still recognise the input as high or low. Normally it will switch at 50% so normally we could call 26.6% to 50% of the supply voltage floating low, and 50% to 73.3% floating high. The implications of this are:
a) that pulses to and from the floating range will only be detected if they cross the switching level for the cmos gate.
b) that TTL pulses to marginal positive levels may not be detected by the pulse detector (but will still show up on the level detectors if they are not too fast)
c) that the pulse detectors will show what users usually want to know, namely whether any transients are going to cause switching in cmos devices. If the probe is floating (that is have an undetermined input) then it will be floating either high or low. If it is floating high then it will not detect a positive going pulse because it is not a true pulse as far as the probe is concerned. Similarly, if it floating low then it will not detect a negative pulse. All these conditions are illustrated in the table and diagrams as below.
4. Logic Probe Circuit Description - Indicators.
The visual indicators are provided by the LED's. The audible indicators are provided by an audio frequency relaxation oscillator driving a piezo element via CMOS inverter buffers. The relaxation oscillator consists of a PUT (programmable unijunction transistor) fed by a variable time constant supply. The PUT acts like an open circuit if the gate voltage is higher than the anode voltage. It avalanches to a short circuit if the anode voltage reached the gate voltage. If any of the indicator signals are high the high charges C5 through the corresponding resistance (R12, R13 or R14.) When the PUT triggers it discharges C5 which restores the PUT and charging recommences. The resistance in the charge circuit determines the charge time which in turn determines the oscillator tone.
HOW TO USE THE LOGIC PROBE
Determine the supply voltage of the logic elements to be tested. Connect the positive and ground (or negative) leads correctly. Place the tip of the probe on the point you want to test. If the circuit has switches to control its operation and you want to see what happens when you change settings hold the probe in place while you make the changes. Be careful not to short out components on the board under test. The indicators will tell you if you are in the immunity band (no signal.) A HIGH level will bring on the RED LED and a high pitched sound. A LOW level will bring a low pitched sound and the GREEN LED. A fast pulse will light the YELLOW LED and a medium pitched sound for about a second. A slow pulse will combine the fast pulse signals with a pulse of the relevant level indicators. A level change will combine the pulse signals with the relevant leval signal. If the level change is very slow the pulse signal may not coincide with the start of the level signal. The Table on the next page lists the typical states and transitions that the logic probe will detect. The Conditions are shown the Diagrams.
LOGIC PROBE ASSEMBLY INSTRUCTIONS
LOGIC PROBE assembly is straight forward and components may be added to the PCB in any order. Note that there are two links to be added to the PCB. The metal probe for the Logic Probe must be soldered to the large pad where indicated underneath the PCB. Use a cut piece of wire from one of the resistors as the probe, Power for the probe is derived from the circuit under test. The GROUND and POSITIVE pads at the right side of the PCB are where power is connected to the board. Two tie holes have been drilled next to each pad so that the wires may be tied down and reduce mechanical strain on the wires as the probe is moved around during use.
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